• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The invention relates to the field of measurement technology and can be used to monitor telephone communication lines. The purpose of the invention — enhanced functionality — is achieved by enabling the generation of sine pulses. J gA V. an ideal signal with flat edges and a fixed potential in the pause between them. The signal generator contains a master oscillator 1, a pulse shaper 2, a comparator 3, keys 4 and 5, modulator 6, operational amplifiers 7, 8 and 13, capacitor 9, current sources 10 and 11, resistors 12 and 14. The modulator 6 inlet The level bias circuit 15, the keys 16 and 17. The drawing also shows the low-pass filters 24 and 26, the band-pass filter 25. The amplifier 7 operates in the comparator mode. The proposed generator provides the generation of pulses of a sinusoidal signal with gentle fronts of a given amplitude, as well as a clear fixation of the pause between pulses at any given potential. 2 hp f-ly, 4 ill. I O): o eat a fug /
    公开号:SU1351526A3
    申请号:SU843791604
    申请日:1984-09-17
    公开日:1987-11-07
    发明作者:Герман Лутгардис Корнелиус Рабай Дирк；Рене Хаспеслаф Дидье
    申请人:Интернэшнл Стандарт Электрик Корпорейшн (Фирма)；
    IPC主号:
    专利说明:

    The invention relates to measurement technology and can be used to monitor telephone communication lines.
    The purpose of the invention is to enhance the functionality by enabling the generation of pulses of a sinusoidal signal with flat edges and a fixed: potential themselves.
    Fig. 1 is a block diagram of a signal generator; Fig. 2 is a pulse diagram of an envelope signal; on fig.Z - comparator; 4 is a pulse diagram of the comparator control signals.
    I.
    The signal generator containing master oscillator 1, the output of which is connected to the input of the imaging unit 2 pulses with direct and inverse outputs, as well as the comparator 3, the first 4 and second 5 keys and the modulator 6, the output of which through the first key is connected to the output of the device through the second key is connected to the reference potential bus, the clock input of the modulator 6 is connected to the second output of the master oscillator 1, and the pulse shaper contains three operational amplifiers 7, the first input of the first of which is connected to the first output of the master generator 1, the second input — with the first input of the second operational amplifier 8. and through the capacitor 9 — with a common bus; and through the first 10 and second 11 current sources — with the second AND third bus of the reference voltage, respectively, the control inputs of the first 10 and second 11 current sources are connected to the output of the first operational amplifier 7, the output of the second operational amplifier 8 is connected to its second input, the first output of the driver 2 and the non-inverting input of the comparator 3 and the first input of the modulator 6, as well as through the first resistor 12 - with the first The third input of the third operational amplifier 13, the second input of which is connected to a common length, and the code to the second output of the formaid and direct outputs of the comparator 3 are connected to the control inputs of the first 4 and second 5 keys, respectively, and the first, second and third control inputs are respectively with the third, fourth and fifth codes of the master oscillator 1.
    In this case, the modulator 6 contains a level bias circuit 15, the input of which
    in the pause between the impulse-10 is connected to the clock input of the modulator of the torus 6, and the first and second outputs are connected to
    control inputs of the first 16 and second 17 keys connected between. corresponding to the input and output of the modulator 6, each key containing n MOS and p MOS transistors, the drain and source terminals of which are combined and are informational switches of the key, and the combined gates of its control input.
    The comparator 3 (fig. 3) contains the first 18 and second 19 inverters connected in a ring, the inputs of which through the first 20 and second 21 keys are connected respectively to the inverting and non-inverting inputs of the comparator, and the outputs to the inverting and non-inverting outputs of the comparator 3, conclusions positive20
    25
    thirty
    power and negative voltages of the first 18 and second 19 inverters are combined and connected to the positive and negative supply buses, respectively, through the third 22
    35 and fourth 23 analog keys, the control inputs of which are connected respectively to the third and second control inputs of the comparator 3, the first control input of which is connected to the control inputs of the first 20 and second 21 keys, the latter being interlocked when the third and fourth keys are open, and vice versa .
    45 In addition, the first low-pass filter 24 (low-pass filter), the band-pass filter 25, the second low pass filter 26 (figure 1) are indicated. .
    The device works as follows.
    The task is to generate pulses of a sinusoidal signal with a frequency of 12 or 16 kHz with a gentle
    The task is to generate pulses of a sinusoidal signal with a frequency of 12 or 16 kHz with a gentle
    bodies 2, the inverting input of the compara- tion by increasing and decreasing the amplitude of the inside and the second input of the modulator 6, the pulse to eliminate the slider, and also through the second resistor 14 - clicks. The minimum length of the pulse with the first input of the third operation (pack) at the full amplitude amplifier 13, and the inverse of the sinusoidal signal is
    The comparator 3 (fig. 3) contains the first 18 and second 19 inverters connected in a ring, the inputs of which through the first 20 and second 21 keys are connected respectively to the inverting and non-inverting inputs of the comparator, and the outputs to the inverting and non-inverting outputs of the comparator 3, conclusions positive0
    power and negative voltages of the first 18 and second 19 inverters are combined and connected to the positive and negative supply buses, respectively, through the third 22
    35 and fourth 23 analog keys, the control inputs of which are connected respectively to the third and second control inputs of the comparator 3, the first control input of which is connected to the control inputs of the first 20 and second 21 keys, the latter being interlocked when the third and fourth keys are open, and vice versa .
    45 In addition, the first low-pass filter 24 (low-pass filter), the band-pass filter 25, the second low pass filter 26 (figure 1) are indicated. .
    The device works as follows.
    The task is to generate pulses of a sinusoidal signal with a frequency of 12 or 16 kHz with a gentle
    100 ms, the interval between pulses is 100 ms (FIG. 2), in the pause between pulses, the output signal of the device must have some fixed amplitude.
    The envelope formation is performed by the keystone generator on the amplifier 7, the capacitor 9, the current sources 10 and 11 from the driving square wave PW with a frequency of 3, 13 Hz (Fig. 2a) produced by the generator 1.
    Amplifier 7 operates in comparator mode. When switching the PW signal, sources 10 and 11 are switched and capacitor 9 is linearly charged by the current of one of these sources to voltage VREF 1 or VREF 2, respectively, which persists until the next switching signal PW at the first output of generator 1. As a result, capacitor 9 and the output of the amplifier 8, a trapezoidal signal, asymmetrical relative to the earth, is formed, varying from VEEF 2 to VREF 1. This signal is inverted by the amplifier 13, resulting in a BS signal (Fig. 26).
    Signals BS + and BS- are fed to the inputs of the modulator 6, to the control input of which a ROM signal of frequency 4096 or 2048 kHz is received. Signals BS + and BS- are alternately connected to the output of the modulator 6, whereby a signal filled with pulses with the frequency of the PDM1 / PDM2 signal is generated (Fig. 2b). The frequency of the latter is chosen so that using filtering it is convenient to isolate oscillations with a frequency of 12 and 16 kHz.
    To determine the pause between pulses, there is a comparator 3, the inputs of which also receive signals BS + and BS-. In accordance with the sign of the difference between these signals, either the output of the modulator 6 with the help of key 4 or, in a pause, a certain fixed potential with the help of key 5 is connected to the output of the device ShTS.
    I
    The difference between the BS + and BS- signals (Fig. 2) is 2VREF1 (in pulse) or 2VREF2 (in pause), otherwise affecting the bias voltage of amplifiers 7 and 8. Choosing VREF2 is significantly greater than the possible bias of the amplifiers, for example VREF2
     -0.7 V, it is possible to completely eliminate the effect of bias on the accuracy of pulse / pause detection by comparator 3, which is an advantage of the proposed device in order to further reduce interference in the communication channel.
    The output of the MNTC processes 0 with a low pass filter 24, a band pass filter 25 and a low pass filter 26. Low pass filter 24 is about the cut-off frequency of 20 kHz and is used to limit the spectrum of the signal. The filter 25 is a sixth-order band-pass filter on switched capacitors, it contains a second-order sequentially connected low-pass filter and, accordingly, a band-pass filter with a passband from 12 to 16 kHz.
    0 works with a clock frequency of 4096 kHz and generates a signal whose spectrum contains the main sinusoidal components of 12 or 16 kHz, arriving at a band-pass filter with a clock frequency of that 256 kHz, where the components are further attenuated, le. frequencies in the working area of the channel-communication frequency. LPF 26 - Rausch filter with a cut-off frequency of 50 kHz, serves
    0 to eliminate switching noise filter 25.
    Comparator 3 (4) ig 3) contains two inverters 18 and 19, the inverters connected in a ring are connected to
    5 position of negative and negative supply voltage through the keys 22 and 23 on the transistors, respectively. Inverters 18 and 19 are connected to the inputs of the comparator through
    0 analog switches 20 and 21 on transistors NM8 and NM9, controlled by the signal PW 1 (Fig. 4), switches 22 and 23 are controlled by the antiphase signals PW 2 and PW 3 (Fig. 46 and b).
    5 All signals vary in a certain interval and have a frequency of 256 kHz.
    When the transition signal PW 1 in 1 input signals of the comparator BS + and
    0 BS-are fed to the inputs of the inverters 18 and 19 and stored on the parasitic input capacitors x. Then the input switches 20 and 21 are closed (PW 1 0) and the keys 22 and 23 are opened (PW 2
    5 O, PW 3 0), both inverters 18 and 19 are connected to the power supply. If BS + is larger than BS-, open transistors 18.2 and 19.1, and this state is maintained by positive feedback (the inverters are connected in a ring).
    Thus, the inverter 18 is set to O, and the inverter 19 is set to 1, the voltages at the outputs are almost equal to + V and -V, and these voltages are applied to the control inputs of the keys 4 and 5. The BS + state is greater than BS- corresponding to the presence pulse and therefore key A opens, and key 5 closes. The signal from the output of the modulator 6 passes to the input of the filter 24. During a pause BS + above the BS-state of the comparator changes from to the opposite, the input of the filter 24 is disconnected from the output of the modulators and the key is connected to some fixed potential.
    The advantage of the proposed signal generator is the possibility of generating pulses of a sinusoidal signal with gentle fronts of a given amplitude, as well as a clear fixation of the pause between pulses at any given potential.
    Formula of the invention of
    权利要求:
    Claims (3)
    [1]
    1. A signal generator comprising a master oscillator, the output of which is connected to an input of a pulse driver, as well as a comparator, characterized in that, in order to extend the functionality by allowing the generation of pulses of a sinusoidal signal with gentle edges and a fixed potential in the pause between the pulses, It is entered into the first and second keys and the modulator, the output of which is connected via the first key to the output of the device, which is connected via the second key to the reference potential bus, tact - the modulator input is connected to the output of the master oscillator, and the pulse generator contains three operational amplifiers, the first input of the first of which is connected to the first output of the master oscillator, the second input to the first input of the second operational amplifier and through a capacitor to the common bus, and through the first and second current sources - from the second and third tires of the reference voltage, respectively, input
    five
    0
    five
    about
    five
    0
    The control signals of the first and second current sources are connected to the output of the first operational amplifier, the output of the second operational amplifier is connected to its second input, to the first Bbw output of the pulse former, the non-inverting input of the comparator and the first input of the modulator, and also through the first resistor to the first input The third operational amplifier, the second input of which is connected to the common length, and the output - to the second output of the pulse shaper, the inverting input of the comparator and the second input of the modulator, as well as through the second cut Torr - to the first input of the third operational amplifier, said inverted and direct outputs of the comparator are connected to the control inputs of the first and second keys, and the first, second and third control inputs - respectively third, fourth and p tm outputs; master oscillator.
    [2]
    2. The generator according to claim 1, characterized in that the modulator contains a level bias circuit, the input of which is connected to the clock input of the modulator, and the first and second outputs are connected to the control inputs of the first and second keys connected between the corresponding input and output of the module A torus, each key contains p MOS and p MOS transistors, the drain and source terminals of which are combined and are informational outputs of the key, and the combined gates - its control input.
    [3]
    3. The generator according to claim 1, about tl and h ayu yi and the fact that the comparator contains the first and second inverters connected in a ring, the inputs of which through the first and second keys are connected respectively to the inverting and non-inverting inputs of the comparator , and outputs with inverting and non-inverting outputs. comparator, the conclusions of the positive and negative voltages of the first and second
    inverters are connected and connected to the positive and negative power buses, respectively, via the third and fourth analog switches, whose control inputs
    connected respectively to the third and second control inputs of the comparator, the first control input of which is connected to the control inputs of the first and second keys, the first and second keys being closed when the third and fourth keys are open, and vice versa, with the first and second inverters
    contain p MOS and p MOS transistors, the gates of which are connected to the input of the inverter, the output of which is connected to the drain n the MOS and source of the MOS transistor, outputting respectively the source and drain of which are connected respectively to the positive and negative buses of the inverter.
    VREFI 35+,.
    ff) -MREPZ
    -UKEP ffs,
    fig 2
    55.
     55 Editor M. Blancar
    Compiled by S. Klevtsov
    Tehred A. Kravchuk Proofreader S. Shekmar
    Order 5302/59 Circulation 900 Subscription
    VNIIPI USSR State Committee
    for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab ,, d.4 / 5
    . Production and printing company, Uzhgorod, Projecto st., 4
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    引用文献:
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    DE1299699B|1967-06-21|1969-07-24|Siemens Ag|Generator for generating trapezoidal voltages|
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    AU4444297A|1996-10-02|1998-04-24|Ericsson Austria Aktiengesellschaft|Remote supply circuitry|
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    优先权:
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